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TDA7580
FM/AM digital IF sampling processor
Features

FM/AM IF sampling DSP ON-CHIP analogue to digital converter for 10.7MHz IF signal conversion FM channel equalization FM adjacent channel suppression Reception enhancement in multipath condition Stereo decoder and weak signal processing 2 Channel serial audio interface (SAI) with sample rate converter I2C and buffer SPI control interfaces RDS filter, demodulator & decoder Inter processor transport interface for antenna and tuner diversity Front-end AGC feedback of an AM/FM channel. The HW & SW architecture has been devised to perform a digital equalization of the FM/AM channel, and a real rejection of adjacent channels and any other signals, interfering with the listening of the desired station. In severe multiple path conditions, the reception is improved to get high quality audio.
LQFP64
Description
The TDA7580 is an integrated circuit implementing an advanced mixed analogue and digital solution, to perform the signal processing Table 1. Device summary
Part number TDA7580 TDA758013TR
Package LQFP64 LQFP64
Packing Tube Tape and reel
March 2007
Rev 5
1/39
www.st.com 1
Contents
TDA7580
Contents
1 2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram and electrical specifications . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 4 5 6 7 8
SAI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 RDS SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BSPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Inter processor transport interface for antenna diversity . . . . . . . . . . 26 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 24 bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Clock generation unit (CGU) and oscillator . . . . . . . . . . . . . . . . . . . . . . . 29 Stereo decoder (HWSTER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 I2C interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Serial peripheral interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 High speed serial synchronous interface (HS3I) . . . . . . . . . . . . . . . . . . . 31 Tuner AGC keying DAC (KEYDAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous sample rate converter (ASRC) . . . . . . . . . . . . . . . . . . . . . 31 IF band pass analogue to digital converter (IFADC) . . . . . . . . . . . . . 31 Digital down converter (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 RDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AM/FM Detector (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/39
TDA7580
Contents
9.1
Electrical application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10 11 12
Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3/39
List of tables
TDA7580
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended DC operating conditions (Tj = -40C to 125C) . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Low voltage interface CMOS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 15 High voltage CMOS interface DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15 Current consumption (Tj =-40C to 125C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Crystal characteristics for 1 and 2 chip load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External clock signal on XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DSP core (Tj =-40C to 125C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 FM stereo decoder characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI and I2C timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SAI Timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 RDS SPI timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BSPI timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 HS3I timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C BUS timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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TDA7580
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PIN connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power on and boot sequence using I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power on and boot sequence using SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SAI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SAI protocol (when: RLRS=0; RREL=0; RCKP=1; RDIR=0) . . . . . . . . . . . . . . . . . . . . . . . 20 SAI protocol (when: RLRS=1; RREL=0; RCKP=1; RDIR=1) . . . . . . . . . . . . . . . . . . . . . . . 21 SAI protocol (when: RLRS=0; RREL=0; RCKP=0; RDIR=0) . . . . . . . . . . . . . . . . . . . . . . . 21 SAI protocol (when: RLRS=0; RREL=1; RCKP=1; RDIR=0) . . . . . . . . . . . . . . . . . . . . . . . 21 RDS SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 RDS SPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 BSPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 BSPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 High speed synchronous serial interface - HS3I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 HS3I clocking scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DSP and RDS I2C BUS timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Radio mode with external slave audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Radio mode with external master audio device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Audio mode with external slave audio device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Application diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Mechanical, data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Overview
TDA7580
1
Overview
The algorithm is self-adaptive, thus it requires no "on-the-field" adjustments after the parameters optimization. The chip embeds a Band Pass Sigma Delta Analogue to Digital Converter for 10.7MHz IF conversion from a "tuner device" (the TDA7515 is highly recommended). The 24bit DSP allows flexibility in the algorithms implementation, thus giving some freedom for customer required features. The total processing power offers a significant headroom for customer's software requirement, even when the channel equalization and the decoding software is running. the program and data memory space can be loaded from an external non volatile memory via I2C or SPI. The oscillator module works with an external 74.1MHz quartz crystal. It has very low electro magnetic interference, as it introduces very low distortion, and in any case harmonics fall outside the radio bandwidth. The companion tuner device receives the reference clock through a differential ended interface, which works off the oscillator module by properly dividing down the master clock frequency. That allows the overall system saving an additional crystal for the tuner. After the IF conversion, the digitized baseband signal passes through the base band processing section, either FM or AM, depending on the listener selection. The FM base band processing comprises of stereo decoder, spike detection and noise blanking. The AM noise blanking is fully software implemented. The internal RDS filter, demodulator and decoder features complete functions to have the output data available through either I2C or SPI interface. No DSP support is needed but at start-up, so that RDS can work in background and in parallel with other DSP processing. This mode (RDS only) allows current consumption saving for low power application modes. An I2C/SPI interface is available for any control and communication with the main micro, as well as RDS data interface. The DSP SPI block embeds a 10 words FIFO for both transmit and receive channels, to lighten the DSP task and frequently respond to the interrupt from the control interface. Serial audio interface (SAI) is the ideal solution for the audio data transfer, both transmit and receive: either master or slave. The flexibility of this module gives a wide choice of different protocols, including I2S. Two fully independent bidirectional data channels, with separate clocks allows the use of TDA7580 as general purpose digital audio processor. A fully asynchronous sample rate converter (ASRC) is available as a peripheral prior to sending audio data out via the SAI, so that internal audio sampling rate (~36kHz and FM/AM mode) can be adapted by upconversion to any external rate. An inter processor transport interface (HS3I, high speed synchronous serial interface) is also available for a modular system which implements Dual Tuner Diversity, thus enhancing the overall system performance. It is about a synchronous serial interface which exchanges data up to the MPX rate. It has been designed to reduce the electro magnetic interference toward the sensitive analogue signal from the tuner. General purpose I/O registers are connected to and controlled by the DSP, by means of memory map. A debug and test interface is available for on chip software debug as well as for internal registers read/write operation.
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TDA7580
Block diagram and electrical specifications
2
Block diagram and electrical specifications
Figure 1. Block diagram
A/D
RDS
I2C/SPI
I2C/SPI HS3I
IF digital Signal processor
DAC
SAI1
SAI0
CGU Oscillator
SRC
Table 2.
Symbol VDD VDD3
Absolute maximum ratings
Parameter Power supplies (1) Nom. 1.8V Nom. 3.3V Value -0.5 to 2.5 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 6.50 -0.5 to 3.80 -0.5 to (VDD+0.5) -0.5 to (VDD3+0.5) -40 to 125 -55 to 150 Unit V V V V V V C C
Analog input or output voltage belonging to 3.3V IO ring (VDDSD, VDDOSC) Digital input or output voltage, 5V tolerant All remaining digital input or output voltage Tj Tstg Operating junction temperature range Storage temperature Normal(2) Failsafe(3) Nom. 1.8V Nom. 3.3V
1. VDD3 refers to all of the nominal 3.3V power supplies (VDDH, VOSC, VDDSD). VDD refers to all of the nominal 1.8V power supplies (VDD, VMTR). 2. During Normal Mode operation VDD3 is always available as specified. 3. During Fail-safe Mode operation VDD3 may be not available.
Warning:
Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
7/39
Block diagram and electrical specifications Table 3.
Symbol VDD VDDH VOSC VDDSD VMTR
TDA7580
Recommended DC operating conditions (Tj = -40C to 125C)
Parameter 1.8V Power supply voltage 3.3V Power supply voltage (1) 3.3V Power supply voltage (1) 3.3V Power supply voltage (1) 1.8V Power supply voltage Comment Core power supply IO Rings power supply (with GNDH) Oscillator power supply (GNDOSC) IF ADC power supply (with GNDSD) DAC keying and tuner clock power supply (with GNDMTR) Min. 1.7 3.15 3.15 3.15 1.7 Typ. 1.80 3.30 3.30 3.30 1.80 Max. 1.9 3.45 3.45 3.45 1.9 Unit V V V V V
1. VDDH, VOSC, VDDSD are also indicated in this document as VDD3. All others as VDD.
Table 4.
Symbol Rth j-amb
Thermal data
Parameter Thermal resistance junction to ambient Value 68 Unit C/W
8/39
TDA7580
Block diagram and electrical specifications
2.1
Pin description
Figure 2. PIN connection (top view)
DBOUT1 DBOUT0 VDDISO VDDSD DBRQ1 DBRQ0 DBCK1 DBCK0 GNDH GNDH DBIN1 DBIN0 VDDH VDDH GND VDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
VHI VCM VLO INP INN VCMOP GNDSD GNDOSC XTI XTO VDDOSC VDDMTR CKREFP CKREFN AGCKEY GNDMTR
49
1 2 3
48 47 46 45 44 43 42
GND VDD TST3_LRCKR TST2_SCKR LRCK_LRCKT SCLK_SCKT SDO0 VDDH GNDH TST1_SDI1 TST4_SDI0 GPIO_SDO1 TESTN GND VDD RESETN
DEBUG1
IFADC
DEBUG0
4 5 6 7 8 10 11 13 14 15 16
17
SAI OSC. Tuner
19 I 2 P/ CR /S D 20 PS
41 40 39 38 37 36 35
9
12
I
D
HS3I
21 22 23 24 25 26 27 28
RDS
29 30 31
INT
S
34 33
32
ADDR_SD
SDA_MOSI
18
RDS_INT
IQCH1
IQCH2
IQCH3
MISO
GND
GNDH
VDD
VDDH
PROTSEL_SS
SCL_SCK
IFADC Modulator Power Supply pins pair Oscillator Power Supply pins pair Tuner Clock Out and AGC Keying DAC Power Supply pins pair Core Logic 1.8V Power Supply pins pair I/O Ring 3.3V Power Supply pins pair
Table 5.
N
Pin description
Name Type Description Notes After Reset
1
VHI
A
It needs external Internally generated IFADC Opamps 2.65V (@VDD=3.3V) reference voltage pin minimum 4.7F ceramic for external filtering capacitor Internally generated common mode 1.65V It needs external (@VDD=3.3V) reference voltage pin for minimum 10F ceramic external filtering capacitor Internally generated IFADC opamps It needs external 0.65V (@VDD=3.3V) reference voltage pin minimum 4.7F ceramic for external filtering capacitor Positive IF signal input from tuner Negative IF signal input from tuner Not connected. 2.0Vpp @VDD=3.3V 2.0Vpp @VDD=3.3V
2
VCM
A
3 4 5 6
VLO INP INN VCMOP
A A A -
RDS_CS
IQSYNC
9/39
Block diagram and electrical specifications Table 5.
N
TDA7580
Pin description (continued)
Name Type Description Notes Clean ground, to be star connected to voltage regulator ground Clean ground, to be star connected to voltage regulator ground Maximum voltage swing is VDD=3.3V After Reset
7
GNDSD
G
IFADC modulator analogue ground
8
GNDOSC
G
Oscillator ground High impedance oscillator input (quartz connection) or clock input when in Antenna Diversity slave mode Low impedance oscillator output (quartz connection) Oscillator power supply Tuner reference clock and AGC keying DAC power supply
9
XTI
I
10 11 12
XTO VDDOSC VDDMTR
O P P
3.3V 1.8V FM 100kHz AMEU 18kHz With internal pull-up, on at reset [PP] FM 100kHz AMEU 18kHz With internal pull-up, on at reset [PP] 1.5kohm 30% output impedance. 1Vpp 1% output dynamic range
13
CKREFP
B
Tuner reference clock positive output.
Output
14
CKREFN
B
Tuner reference clock negative output.
Output
15
AGCKEY
A
DAC output for Tuner AGC keying Ground of the tuner reference clock buffer and the AGC keying DAC DSP0 GPIO for control serial interface (low: SPI or high: I2C) selection at device Bootstrap. In SPI protocol mode, after boot procedure, SPI slave select, otherwise DSP0 GPIO0 Control serial interface and RDS IO: - SPI mode: slave data in or master data out for main SPI & RDS SPI data in - I2C mode: data for main I2C or RDS I2C SPI slave data out or master data in for main SPI and RDS SPI data out
16
GNDMTR
G
17
PROTSEL_SS
B
DSP0 GPIO0 5V tolerant With internal pull-up, on at reset [PP]
Input
18
SDA_MOSI
B
5V tolerant With internal pull-up, on at reset [PP] DSP0 GPIO1 5V tolerant. With internal pull-up, on at reset [PP] 5V tolerant. With internal pull-up, on at reset [PP]
Input
19
MISO
B
Input
20
SCL_SCK
B
Bit clock for Control Serial Interface and RDS
Input
10/39
TDA7580 Table 5.
N 21 22 GND VDD
Block diagram and electrical specifications Pin description (continued)
Name Type G P Description Digital core power ground Digital core power supply High speed synchronous serial interface (HS3I) clock if HS3I master mode, else DSP1 GPIO or DSP1 debug port clock (DBOUT1) High speed synchronous serial interface (HS3I) channel 1 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port request (DBRQ1) High speed synchronous serial interface (HS3I) channel 2 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port data In (DBIN1) High speed synchronous serial interface (HS3I) channel 3 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port data out (DBCK1) 3.3V IO ring power supply (HS3I, I2C/SPI, RDS, INT) 3.3V IO ring power ground (HS3I, I2C/SPI, RDS, INT) RDS interrupt to external main microprocessor in case of traffic information DSP1 GPIO4. 5V tolerant, open drain With internal pull-up, on at reset [OD] 1.8V DSP1 GPIO0 5V tolerant. With internal pull-up, on at reset DSP1 GPIO1 5V tolerant. With internal pull-up, on at reset [PP] DSP1 GPIO2 5V tolerant. With internal pull-down, on at reset [PP] DSP1 GPIO3 5V tolerant With internal pull-down, on at reset [PP] Notes After Reset
23
IQSYNC
B
Input
24
IQCH1
B
Input
25
IQCH2
B
Input
26
IQCH3
B
Input
27 28
VDDH GNDH
P G
29
RDS_INT
B
Input
30
RDS_CS
B
RDS chip select. When RESETN rising, If DSP1 GPIO5. 5V RDS_CS 0, the RDS's SPI is selected; tolerant. With internal else RDS's I2C pull-up, on at reset [PP] DSP0 external interrupt IFS chip master (Low) or slave (High) mode selection, latched in upon RESETN release. It selects the LSB of the I2C addresses. Station detector output Chip hardware reset, active low Digital power supply Digital power ground Test enable pin, active low With internal pull-up 5V tolerant. With internal pull-up, on at reset DSP0 GPIO2 5V tolerant With internal pull-down, on at reset [PP] 5V tolerant With internal pull-up 1.8V
Input
31
INT
I
32
ADDR_SD
B
Input
33 34 35 36
RESETN VDD GND TESTN
I P G I
11/39
Block diagram and electrical specifications Table 5.
N
TDA7580
Pin description (continued)
Name Type Description DSP0 GPIO for boot selection or audio SAI0 output. Notes 5V tolerant. DSP0 GPIO3. With internal pull-up, on at reset [PP] After Reset Input
37
GPIO_SDO1
B
38
TST4_SDI0
B
5V tolerant. DSP0 Audio SAI0 data input or test selection pin GPIO5. With internal in test mode pull-up, on at reset [PP] DSP0 GPIO for boot selection or audio SAI1 input. Test selection pin in test mode. 3.3V IO ring power ground (audio SAI, ResetN, test pins) 3.3V IO ring power supply (audio SAI, ResetN, test pins) Radio or audio SAI0 data output SAI0 receive and transmit bit clock (master or slave with ASRC); SAI1 transmit bit clock SAI0 receive and transmit left/right clock (master or slave with ASRC); SAI1 transmit left/right clock SAI0 Transmit bit clock; SAI1 receive and transmit bit clock. Or test selection pin in test mode SAI0 Transmit LeftRight clock; SAI1 Receive and Transmit bit clock. Or Test selection pin in Test Mode Digital core power supply Digital core power ground DSP0 GPIO. 9. 5V tolerant. With internal pull down, on at reset [PP] DSP0 GPIO. 11. 5V tolerant. With internal pull down, on at reset [PP] DSP0 GPIO. 5V tolerant With internal pull up, on at reset [PP] DSP0 GPIO10. 5V tolerant. With internal pull up, on at reset [PP] 5V tolerant. With internal pull up, @0V at reset [PP] 5V tolerant With internal pull up, on at reset [PP] 5V tolerant With internal pull up, on at reset [PP] 5V tolerant. DSP0 GPIO6. With internal pull up, on at reset [PP] DSP0 GPIO7. 5V tolerant. With internal pull up, on at reset [PP] 1.8V 5V tolerant. DSP0 GPIO4. With internal pull-up, on at reset [PP]
Input
39
TST1_SDI1
B
Input
40 41
GNDH VDDH
G P
42
SDO0
B
Output
43
SCLK_SCKT
B
Input
44
LRCK_LRCKT
B
Input
45
TST2_SCKR
B
Input
46 47 48
TST3_LRCKR VDD GND
B P G
Input
49
DBCK0
B
Debug port clock of DSP0 (DBCK0)
Input
50
DBIN0
B
Debug port data input of DSP0 (DBIN0)
Input
51
DBRQ0
B
Debug port request of DSP0 (DBRQ0)
Input
52
DBOUT0
B
Debug port data output of DSP0 (DBOUT0)
Input
12/39
TDA7580 Table 5.
N 53 54 GNDH VDDH
Block diagram and electrical specifications Pin description (continued)
Name Type G P Description 3.3V IO ring power ground (debug interface, GPIO) 3.3V IO ring power supply (Debug interface, GPIO) DSP1 debug port clock (DBCK1) if HS3I master mode, else high speed synchronous serial interface (HS3I) channel3 data DSP1 GPIO or DSP1 debug port data in (DBIN1) if HS3I master mode, else high speed synchronous serial interface (HS3I) channel2 data i DSP1 GPIO9. 5V tolerant. With internal pull down, on at reset [PP] DSP1 GPIO11 5V tolerant With internal pull down, on at reset [PP] Notes After Reset
55
DBCK1
B
Input
56
DBIN1
B
Input
57
DBRQ1
B
DSP1 GPIO or DSP1 debug port request 5V tolerant. With (DBRQ1) if HS3I master mode, else high internal pull up, on at speed synchronous serial interface (HS3I) reset [PP] channel1 data DSP1 GPIO or DSP1 debug port data out (DBOUT1) if HS3I master mode, else high speed synchronous serial interface (HS3I) clock Digital core power supply Digital core power ground 3.3V N-isolation biasing supply 3.3V IO ring power ground (modulator digital section) 3.3V IO ring power supply (modulator digital section) 3.3V IFADC modulator analogue power supply Clean power supply, to be star connected to 3.3V voltage regulator Clean 3.3V supply to be star connected to voltage regulator DSP1 GPIO10 5V tolerant With internal pull up, on at reset [PP] 1.8V
Input
58
DBOUT1
B
Input
59 60 61
VDD GND VDDISO
P G P
62 63
GNDH VDDH
G P
64
VDDSD
P
I/O Type P: Power supply from voltage regulator G: Power ground from voltage regulator A: Analogue I/O I: Digital input O: Digital output B: Bidirectional I/O
I/O Definition and status Z: high impedance (input) O: logic low output X: undefined output 1: logic high output Output PP: Push pull / OD: Open drain
13/39
Block diagram and electrical specifications
TDA7580
2.2
Table 6.
Symbol lilh lihh lil lih Iipdh Iopuh Iopul Iaihop
Electrical characteristics
General interface electrical characteristics (Tj =-40C to 125C; VDD=1.8V, VDD3= 3.3V)
Parameter Low level input current I/Os@VDD3 (absolute value) High level input current I/Os@VDD3 (absolute value) Low level input current I/Os@VDD (absolute value) High level input current I/Os@VDD (absolute value) Pull-down current I/Os @ VDD3 Pull-up current I/Os @ VDD3 Pull-up current I/Os @ VDD Test condition Vi = 0V (1) (2) without pull-up-down device Vi = VDD3 (1) (2) without pull-up-down device Vi = 0V (1) (3) (4) without pull-up-down device Vi = VDD (1) (3) (4) without pull-up device Vi = VDD3 (5) with pull-down device Vi = 0V (6) with pull-up device Vi = 0V
(3) with
Min.
Typ.
Max. 1 1 1 1
Unit A A A A A A A mA mA mA mA mA mA A A A mA A A A A mA V
35 -100 -40 0.95 -6.25 6.0 -10.0 3.75
60 -70 -30 1.25 -5.0 8.0 -8.0 5.0
85 -40 -20 1.55 -3.75 10.0 -6.0 6.25
pull-up device
Analogue pin sunk / drawn current Vi = VDD3 on pin1 Vi = 0V Analogue pin sunk / drawn current Vi = VDD3 on pin 2 Vi = 0V Analogue pin sunk / drawn current Vi = VDD3 on pin 3 Vi = 0V Analogue pin sunk / drawn current Vi = VDD3 on pin 4 and pin 5 Vi = 0V Analogue pin current on pin 6 Vo = 0V or VDD3
Iacm
Iail
-1.55 -1.25 -0.95 24 -40 32 -32 40 -24 5 0.8 1.2 1.6 1 1 1 80 200 2000
Iain Iaih6 Iaik Ioz IozFT Ilatchup Vesd
Analogue pin sunk / drawn current Vi = VDD on pin 15 Vi = 0V (spec absolute value) Tri-state output leakage 5V tolerant tri-state output leakage I/O latch up current Electrostatic protection Vo = 0V or VDD3 without pull up / down device (1) Vo = 0V or VDD (1) Vo = 5V V < 0V, V > VDD Leakage, 1A
1. The leakage currents are generally very small, <1nA. The value given here, 1mA, is the maximum that can occur after an electrostatic stress on the pin. 2. On pins: 17 to 20, 23 to 26, 29 to 33, 36 to 39, 42 to 46, 49 to 52, 55 to 58. 3. On pins: 13 and 14. 4. Same check on the analogue pin 15 (physically without pull-up-down) 5. On pins: 25, 26, 32, 49, 50, 55, 56 6. On pins: 17 to 20, 23 to 24, 29 to 31, 33, 36 to 39, 42 to 46, 51, 52, 57, 58
14/39
TDA7580 Table 7.
Symbol Vil Vih Vol Voh
Block diagram and electrical specifications Low voltage interface CMOS DC electrical characteristics (Tj =-40C to 125C; VDD3= 3.3V)
Parameter Low level input voltage High level input voltage Low level output voltage High level output voltage Test condition 1.70V<=VDD<=1.90V 1.70V<=VDD<=1.90V Iol = 4mA
(1)
Min.
Typ.
Max. 0.2*VDD
Unit V V
0.8*VDD 0.15 VDD-0,15
V V
Iol = -4mA (1)
1. It is the source/sink current under worst case conditions and reflects the name of the I/O cell according to the drive capability.
Table 8.
Symbol Vil Vih Vol Voh
High voltage CMOS interface DC electrical characteristics (Tj =-40C to 125C; VDD=1.8V)
Parameter Low level input voltage High level input voltage Low level output voltage High level output voltage Test condition 3.15V<=VDD3<=3.45V 3.15V<=VDD3<=3.45V Iol = XmA
(1) (2) (1) (2)
Min.
Typ.
Max. 0.8
Unit V V
2.0 0.15 VDD3-0.15
V V
Iol = -XmA
1. It is the source/sink current under worst case conditions & reflects the name of the I/O cell according to the drive capability 2. X=4mA for pins 17 to 20, 29, 30, 32, 37 to 39, 42 to 46; X=8mA for pins 23 to 26, 49 to 52, 55 to 58.
Table 9.
Symbol IDD IDDHdc IDDHac ISD IOSCdc IOSCac IMTR
Current consumption (Tj =-40C to 125C)
Parameter Current through VDD power supply Static current through VDDH power supply Current through VDDH power supply Current through VSD power supply Current through VOSC power supply Current through VOSC power supply Current through VMTR power supply Test condition VDD=1.8V,VDD3=3.3V All digital blocks working VDD=1.8V,VDD3=3.3V VDD=1.8V,VDD3=3.3V I/Os working with 5pF load VDD=1.8V,VDD3=3.3V VDD=1.8V,VDD3=3.3V without quartz VDD=1.8V,VDD3=3.3V with quartz VDD=1.8V,VDD3=3.3V 25 5.5 6.5 0.5 35 8 9 1.3 10 Min. Typ. 120 13 Max. 150 16 50 45 10.5 11.5 2.0 Unit mA mA mA mA mA mA mA
Note:
74.1MHz internal DSP clock, at Tamb = 25C. Current due to external loads not included.
15/39
Block diagram and electrical specifications Table 10.
Symbol FOSCFM
TDA7580
Oscillator characteristics (Tj =-40C to 125C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V)
Parameter Oscillator frequency (XTI/XTO) Test condition Min. Typ. 74.1 Max. Unit MHz
Note:
The accuracy depends on the quartz frequency precision: high stability oscillator Table 11. Crystal characteristics for 1 and 2 chip load
Parameter value Parameter name 1 chip load Temperature range Adjustment tolerance (@ 25C 3C) Frequency stability (-20C/+70C) Aging @ 25C Shunt (static) capacitance [Co] Motional capacitance Mode of oscillation Resonance resistance Capacitive load for oscillation frequency = 74.1MHz -55C/125C 30 ppm 50 ppm 5 ppm/year <5pF 1fF 30% AT-3rd < 75 ohm 10pF 2 chips load -55C/125C 30 ppm 50 ppm 5 ppm/year <5pF 1fF 30% AT-3rd < 45 ohm 12pF
Table 12.
External clock signal on XTI (In case the device is driven by an external clock through the XTI pin, the characteristics reported in this table have to be met)
Parameter value Parameter name Min Clock frequency Typ 74.10 -50 50 10 5 220 0.50 45
(1)
Max
Unit MHz ppm ps rms ms mV rms V p-p % ps
Frequency stability (-20C/+70C) Clock jitter Start up time Clock level (sine wave) (1) Clock level (square wave)
(1)
640 1.80 55 500
Clock duty cycle (square wave) Clock rise / fall time (square wave)
1. specified @ XTI pin of TDA7580
16/39
TDA7580 Table 13.
Symbol FdspMax
Block diagram and electrical specifications DSP core (Tj =-40C to 125C)
Parameter Maximum DSP clock frequency Test condition VDD=1.7V, VDD3= 3.3V Min. 81.5 Typ. Max. Unit MHz
Table 14.
FM stereo decoder characteristics (Tj =-40C to 125C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V; BW for measurements 20Hz to 15KHz)
Parameter Channel separation Total harmonic distortion Test condition (Adjustble by SW from 0 to -45dB) 1KHz; mono; f=75KHz; 1KHz; mono; f=40KHz; 78 Min. -45 0.02 80 Typ. Max. 0 0.04 82 Unit dB % dB
Symbol a_ch THD
(S+N)/N Signal plus noise to noise ratio
MCK = 18.525MHz, Fsin/Fsout = 0.820445366 Table 15. Sample rate converter (Tj =-40C to 125C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V); BW for measurements 20Hz to 20KHz
Parameter Test condition 20Hz to 20kHz, full scale, 16 bit inp. 20Hz to 20kHz, full scale, 20 bit inp. 1 kHz full scale, 16 bit inp. 2 kHz full scale, 16 bit inp. 5 kHz full scale, 16 bit inp. 10 kHz full scale, 16 bit inp THD+N Total harmonic distortion + noise 15 kHz full scale, 16 bit inp 1 kHz full scale, 20 bit inp. 2 kHz full scale, 20 bit inp. 5 kHz full scale, 20 bit inp. 10 kHz full scale, 20 bit inp 15 kHz full scale, 20 bit inp Dynamic Range DR fratio = 0.82 Rp Fratio Pass band ripple Sampling frequency in/out ratio 1 kHz -60 dB - 24 bit inp. A-weighted from 20Hz to 15kHz Fsout = 44.1 kHz 0.7 141 145 0.4 0.5 1.13 dB dB 1 kHz -60 dB - 16 bit inp. A-weighted 97 -98 -119 -116 -112 -108 -105 100 -95 -116 -113 -109 -105 -102 dB dB dB dB dB dB dB Min. Typ. -95 -98 -98 -98 -98 -98 Max. -92 -95 -95 -95 -95 -95 Unit dB dB dB dB dB dB
Symbol
17/39
Block diagram and electrical specifications Figure 3. Power on and boot sequence using I2C
TDA7580
VDD3 VDD INT RESETN ADDR_SD PROTSEL_SS RDS_CS GPIO_SDO1 TST1_SDI1 SDA_MOSI tint
tvdd3 tvdd
I2C/SPI SLAVE=1 I2C/SPI MASTER=0 IFS SLAVE=1 IFS MASTER=0
Boot
RDS init
SW download
Tuner data
Data
trhd trsu treson tseq
tsw
tdat
ttun
Figure 4.
Power on and boot sequence using SPI
VDD3 VDD INT RESETN ADDR_SD PROTSEL_SS RDS_CS GPIO_SDO1 TST1_SDI1 SDA_MOSI
tint
tvdd3 tvdd
I2C/SPI SLAVE=1 I2C/SPI MASTER=0 IFS SLAVE=1 IFS MASTER=0
Boot
RDS init
SW download
Tuner data
Data
trhd trsu treson tseq
tsw
tdat
ttun
18/39
TDA7580 Table 16.
Timing tvdd3 tvdd tint treson trsu trhd tseq tsw ttun tdat Rise time of 3.3V supply Rise time of 1.8V supply Maximux delay for INT signal
Block diagram and electrical specifications SPI and I2C timing table (Tj =-40C to 125C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V)
Description Min 1 1 40 250 250 4 30 1 1 Typ 13 6 Max 25 10 1 Unit ms ms ms ms s s ms s s s
Minimum RESETN hold time at 0 after the start-up Minimum data set-up time Minimum data hold time Minimum wait time including boot Minimum wait time before downloading the program software Minimum wait time before downloading the software to the FE Minimum wait time before using interface protocols
19/39
SAI Interface
TDA7580
3
SAI Interface
Figure 5. SAI Timings
SDI0-1
Valid
LRCKR
Valid
SCKR
(RCKP=0)
tlrs tdt tsckpl tsdis
tlrh tsdih tsckph tsckr
Table 17.
SAI Timing table (Tj =-40C to 125C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload The values on the table are consistent with a capacitance load on SAI lines of 160pF
Description Clock Cycle SCKR active edge to data out valid LRCK setup time LRCK hold time SDI setup time SDI hold time SCK high time SCK low time Min 302 48 25 25 65 65 146 146 Typ Max 976 65 Unit ns ns ns ns ns ns ns ns
Timing tsckr tdt tlrs tlrh tsdis tsdih tsckph tsckpl
Note:
TDSP = DSP master clock cycle time = 1/FDSP Figure 6. SAI protocol (when: RLRS=0; RREL=0; RCKP=1; RDIR=0)
LRCKR SCKR
LEFT
RIGHT
SDI0-1
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
20/39
TDA7580 Figure 7. SAI protocol (when: RLRS=1; RREL=0; RCKP=1; RDIR=1)
SAI Interface
LRCKR SCKR
LEFT
RIGHT
SDI0-1
MSB(n-1)
LSB(n)
LSB+1(n)
LSB+2(n)
Figure 8.
SAI protocol (when: RLRS=0; RREL=0; RCKP=0; RDIR=0)
LRCKR
SCKR
LEFT
RIGHT
SDI0-1
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
Figure 9.
SAI protocol (when: RLRS=0; RREL=1; RCKP=1; RDIR=0)
LRCKR
SCKR
LEFT
RIGHT
SDI0-1
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
21/39
RDS SPI interface
TDA7580
4
RDS SPI interface
Figure 10. RDS SPI timings
SS
MISO MOSI
Valid
SCL
(CPOL=0,CPHA=0)
tdtr
tsetup tsssetup tsclkl
thold
tsshold tssw
tsclkh tsclk
Table 18.
RDS SPI timing table (Tj =-40C to 125C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload The values on the table are consistent with a capacitance load on RDS SPI lines of 80pF
Description Slave configured Min Typ Max Unit
Symbol
tsclk tdtr tsetup thold tsclkh tsclkl tsssetup tsshold tssw
Clock cycle Sclk edge to MISO valid MOSI setup time MOSI hold time SCK high time width SCK low time width SS setup time SS hold time SS pulse width
1240 239 255 365 620 620 620 620 1240 365
ns ns ns ns ns ns ns ns ns
22/39
TDA7580 Figure 11. RDS SPI clocking scheme
RDS SPI interface
SS(#17)
(CPOL=0,CPHA=0)
SCK(#20)
SCK(#20) SCK(#20)
(CPOL=0,CPHA=1)
(CPOL=1,CPHA=0)
SCK(#20)
(CPOL=1,CPHA=1)
MISO(#19) MOSI(#18)
MSB
6
5
4
3
2
1
0
23/39
BSPI interface
TDA7580
5
BSPI interface
(Tj =-40C to 125C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload The values on the table are consistent with a capacitance load on BSPI lines of 160pF) Figure 12. BSPI timings
SS
MISO MOSI
Valid
SCL
(CPOL=0,CPHA=0)
tdtr
tsetup tsssetup tsclkl
thold
tsshold
tssw
tsclkh tsclk
Table 19.
Symbol
BSPI timing table
Description Min Typ Max Unit
Master configured tsclk tdtr tsetup thold tsclkh tsclkl tsssetup tsshold tssw Clock cycle Sclk edge to MOSI valid MISO setup time MISO hold time SCK high time SCK low time SS setup time SS hold time SS pulse width 184 61 52 52 92 92 92 92 184 92 ns ns ns ns ns ns ns ns ns
Slave configured tsclk tdtr tsetup thold tsclkh tsclkl tsssetup tsshold tssw Clock cycle Sclk edge to MISO valid MOSI setup time MOSI hold time SCK high time SCK high low SS setup time SS hold time SS pulse width 238 88 65 65 119 119 119 119 238 119 ns ns ns ns ns ns ns ns ns
24/39
TDA7580 Figure 13. BSPI clocking scheme
BSPI interface
SS(#17)
(CPOL=0,CPHA=0)
SCK(#20)
SCK(#20) SCK(#20)
(CPOL=0,CPHA=1)
(CPOL=1,CPHA=0)
SCK(#20)
(CPOL=1,CPHA=1)
MISO(#19) MOSI(#18)
MSB
6
5
4
3
2
1
0
25/39
Inter processor transport interface for antenna diversity
TDA7580
6
Inter processor transport interface for antenna diversity
(Tj =-40C to 125C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload. The values on the table are consistent with a capacitance load on HS3I lines of 20pF Figure 14. High speed synchronous serial interface - HS3I
Master Bit Clock
Master Data Out
M2
M3 256 cycles of 74.1MHz
Master Synch
Slave Data Out
S0
S1
S2
S3
Figure 15. HS3I clocking scheme
tmbco tmbcs tsdos
Master Bit Clock tmbcc Master Data Out
Master Synch
Slave Data Out
Table 20.
Timing tsclk tdtr tsetup thold
HS3I timing table
Description MBC clock cycle MBC active edge to master data out valid MBC active edge to master synch valid Slave data out setup time Min 107.95 4 4 6 Typ Max 107.97 Unit ns ns ns ns
Note:
TDSP = DSP master clock cycle time = 1/FDSP
26/39
TDA7580
I2C timing
7
I2C timing
Figure 16. DSP and RDS I2C BUS timings
Table 21.
I2C BUS timing table (Tj =-40C to 125C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V)
Parameter Test condition Standard mode I2C BUS Min. Max. 100 - Fast mode I2C BUS Min. 0 1300 Max. 400 - kHz ns Unit
Symbol
FSCL tBUF
SCLl clock frequency Bus free between a stop and start condition Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated start condition DATA hold time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Data set-up time Capacitive load for each bus line Cb in pF Cb in pF
0 4800
tHD:STA tLOW tHIGH tSU:STA tHD:DAT tR tF tSU;STO tSU:DAT Cb
4800 4800 4800 4800 0 - - 4800 250 10
- - - - 300 300 - - 400
600 1300 600 600 0 12+0.1Cb 12+0.1Cb 600 250 10
- - - - 900 300 300 - - 400
ns ns ns ns ns ns ns ns ns pF
27/39
Functional description
TDA7580
8
Functional description
The TDA7580 IC offers a solution for high performance FM/AM car radio receivers. The high processing power allows audio processing of both internal and external audio source. The processing engine is based on a 24bit programmable DSP, with separate banks of program and data RAMs. A number of hardware modules (peripherals) help in the algorithm implementation of channel equalization and FM/AM baseband post processing. The HW architecture allows to perform dual tuner diversity. In this case two TDA7580 are needed: one device must be configurated as master, generates the clock and controls the main data interfaces. The second device becomes the slave and converts the second IF path, as well as helps the first chip as co-processor.
8.1
24 bit DSP core
Some capabilities of the DSP are listed below:

Single cycle multiply and accumulate with convergent rounding and condition code generation 24 x 24 to 56-bit MAC Unit Double precision multiply Scaling and saturation arithmetic 48-bit or 2 x 24-bit parallel moves 64 interrupt vector locations Fast or long interrupts possible Programmable interrupt priorities and masking Repeat instruction and zero overhead DO loops Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts / subroutines Bit manipulation instructions possible on all registers and memory locations, also jump on bit test 4 pin serial debug interface Debug access to all internal registers, buses and memory locations 5 word deep program address history FIFO Hardware and software breakpoints for both program and data memory accesses Debug single stepping, instruction injection and disassembly of program memory
28/39
TDA7580
Functional description
8.2
DSP peripherals

Clock generation unit (CGU) Stereo decoder (HWSTER) Serial audio interface (SAI) Tuner AGC keying DAC (KEYDAC) Programmable I/O interface (I2C/BSPI) Asynchronous sample rate converter (ASRC) IF band pass sigma delta modulator (IFADC) Digital down converter (DDC) Discriminator (CORDIC) RDS Tuner diversity HS3I
The peripherals are mapped in the X memory space. Most of them can be handled by interrupt, with software programmable priority. Peripherals running at very high rate have direct access to X and Y data bus for very fast movement from or to the core, by mean of single cycle instruction.
8.3
Clock generation unit (CGU) and oscillator
This unit is responsible for supplying all necessary clocks and synchronization signals to the whole chip. The control status register of this unit contains information about the current working mode (oscillator [master mode] or clock buffer [slave mode]), the tuner clock frequency setting, the general setup of the oscillator. This last function is performed inside the CGU, that establishes using a self trimming algorithm, which is the current values that can bias the oscillator: this feature lets the oscillator be independent from process parameters variation. The values of bias current are stored in the control status register of the CGU: 4 bits for the coarse current steps and 6 bits for the fine current steps. In slave mode the oscillator behaves as a buffer: the chip can be then driven using an external clock. The clock divider, placed in this unit, generates the tuner the reference clock and can be programmed for frequencies down to 9KHz with selectable duty cycle and from 4.4Hz to 9KHz with duty cycle 50%. An external clock can drive the XTI pin (please see Table 12 for reference).
8.4
Stereo decoder (HWSTER)
The fully digital hardware stereo decoder does all the signal processing necessary to demodulate an FM MPX signal which is prepared by the channel equalization algorithm in the digital IF sampling device, providing pilot tone dependent mono/stereo switching, as well as stereo-blend and highcut functionality. Selectable de-emphasis time constant allow the use of this module for different FM radio receiver standards.
29/39
Functional description
TDA7580
There are built in filters for field strength processing. In order to obtain the maximum flexibility the field strength processing and noise cancellation, however, are implemented as software inside the programming DSP, which has to provide control signals for the stages softmute, stereoblend, and highcut.
8.5
Serial audio interface (SAI)
The two SAI modules have been embedded in such a way great flexibility is available in their use. The two modules are fully separate and they each have a receive and a transmit channel, as well as they can be selected as either master or slave. The bit clocks and left & right clocks are routed through the pins, so the audio interface can be chosen to be adapted to a large variety of application. One SAI transmit channel can have the asynchronous sample rate converter in front, thus separate different audio rate domains. Additional feature are:

support of 16/24/32 bit word length programmable left/right clock polarity programmable rising/falling edge of the bit clock for data valid programmable data shift direction, MSB or LSB received / transmitted first
8.6
I2C interfaces
The inter integrated circuit bus is a single bidirectional two wire bus used for efficient inter IC control. All I2C bus compatible devices incorporate an on-chip interface which allows them communicate directly with each other via the I2C bus. Every component hooked up to the I2C bus has its own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and /or transmitter on its functionality. Two pins are used to interface both I2C of the DSP and RDS, which have different internal I2C address, thus reducing the on board pin interconnections.
8.7
Serial peripheral interfaces
The DSP and RDS can have this serial interface, alternative to the I2C one. DSP and RDS SPI modules have separate pin for chip select. The DSP SPI has a ten 24 bit words deep FIFO for both receive and transmit sections, which reduces DSP processing overhead even at high data rate. The serial interface is needed to exchange commands and data over the LAN. During an SPI transfer, data is transmitted and received simultaneously. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device. When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin. The central element in the SPI
30/39
TDA7580
Functional description system is the shift register and the read data buffer. The system is single buffered in the transfer direction and double buffered in the receive direction.
8.8
High speed serial synchronous interface (HS3I)
The high speed serial synchronous interface is a module to send and receive data at high rate (up to 9.25Mbit/s per channel) in order to exchange data between 2 separate TDA7580 chip. The exchanged data are related to signals that are used to increase reception quality in car radio systems, which make use of antenna diversity based upon two separate antenna and tuner sections. The channel synchronization clock has a programmable duty cycle, so to reduce in band harmonics noise.
8.9
Tuner AGC keying DAC (KEYDAC)
This DAC provides the front-end tuner with an analogue signal to be used to control the automatic gain controlled stage, thus giving all time the best voltage dynamic range at the IFADC input.
8.10
Asynchronous sample rate converter (ASRC)
This hardware module provides a very flexible way to adapt the internal audio rate, to the one of an external source. It does not require further work off the DSP. There is no need to explicitly configure the input and the output sample rates, as the ASRC solves this problem with an automatic digital ratio locked loop. Main features are:

Automatic tracking of sample frequency Fully digital ratio locked loop Sampling clock jitter rejection Up conversion up to 1:2 Ratio Linear phase
8.11
IF band pass analogue to digital converter (IFADC)
The IFADC is a band pass Sigma Delta A to D converter with sampling rate of 37.05MHz (nominal) and notch frequency of 10.7MHz. The structure is a second order switched capacitor multi bit modulator with self calibration algorithm to adjust the notch frequency. The differential ended input allows 4.0Vpp voltage dynamic range, and reduces the inferred noise back to the previous stage (tuner), and in turn gives high rejection to common mode noises. The high linearity (very high IMD) is needed to fulfill good response of the channel equalization algorithm. Low thermal and 1/f noise assures high dynamic range.
31/39
Functional description
TDA7580
8.12
Digital down converter (DDC)
The DDC module allows to evaluate the in-phase and quadrature components of the incoming digital IF signal. The I and Q computation is performed by the DDC block, which at the same time shifts down to 0-IF frequency the incoming digital signal. After the down conversion the rate is still very high (at the 37.05MHz rate); a SincK filter samples data down by a factor of 32, decreasing it to 1.1578MHz. An additional decimation is performed by the subsequent FIR filters, thus lowering the data rate at the final 289.45kHz, being the MPX data rate.
8.13
RDS
The RDS block is an hardware cell able to process RDS/RBDS signal, intended for recovering the inaudible RDS/RBDS information which are transmitted by most of FM radio broadcasting stations. It comprises of the following:

Demodulation of the european radio data system (RDS) Demodulation of the US radio broadcast data system (RDBS) Automatic group and block synchronisation with flywheel mechanism Error detection and correction RAM buffer with a storage capacity of 24 RDS blocks and related status information I2C and SPI interface, with pins shared with the DSP I2C/SPI
After filtering the oversampled MPX signal, the RDS/RDBS demodulator extracts the RDS data clock, RDS data signal and the quality information. The following RDS/RBDS decoder synchronizes the bitwise RDS stream to a group and block wise information. This processing also includes error detection and error correction algorithms. In addition, an automatic flywheel control avoids exhausting the data exchange between RDS/RDBS processor and the host.
8.14
AM/FM Detector (CORDIC)
The AM/FM detector is a fully programmable peripheral used to detect the phase, amplitude and frequency information of an input complex signal (in-phase and quadrature signals). It can be used to demodulate PM, AM and FM modulated signals. The detection is performed using a high accuracy CORDIC algorithm, working essentially as a cartesian to polar transformer. Four CORDICs are available to allow concurrent software calls.
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TDA7580
Application diagrams
9
Application diagrams
Figure 17. Radio mode with external slave audio DAC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
1 2 3 4 5 6 7 8 9
TST3_LRCKR TST2_SCKR LRCK_LRCKT SCLK_SCKT SDO0
49
48 47 46 45 44 43 42 41 40 1 8 7 6 5
TDA7580
Fs=36kHz
2 3 4
10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 16
TST1_SDI1 39 TST4_SDI0 38 GPIO_SDO1 37
36 35 34 33 29 30 31 32
TDA7535
Dual DAC
In this mode an external slave stereo DAC, like the ST TDA7535, can be easily connected and the TDA7580 outputs the audio from radio station at 36kHz rate. Figure 18. Radio mode with external master audio device
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
1 2 3 4 5 6 7 8 9
TST3_LRCKR 46 TST2_SCKR LRCK_LRCKT SCLK_SCKT SDO0
45 44 43 42 41 40 1 2 3
49
48 47
TDA7580
Fs
4
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
TST1_SDI1 39 TST4_SDI0 38 GPIO_SDO1 37
36 35 34 33 29 30 31 32
External Audio Receiver with its owned audio rate Fs
An external digital audio device is connected externally as a digital audio master, and the internal TDA7580 sample rate converter is responsible for the conversion from internal 36kHz to the external audio rate.
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Application diagrams Figure 19. Audio mode with external slave audio device
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
TDA7580
1 2 3 4 5 6 7 8 9
48 47
TST3_LRCKR 46 TST2_SCKR LRCK_LRCKT SCLK_SCKT SDO0
45 44 43 42 41 40 1 2 3 4 1 2 3 4
CD Player Fs=44.1kHz
8 7 6 5 8 7 6 5
TDA7580
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
TST1_SDI1 39 TST4_SDI0 38 GPIO_SDO1 37
36 35 34 33 28 29 30 31 32
Fs=44.1kHz
TDA7535
Analog In ADC
The 2 stereo channel serial audio interface of the TDA7580 chip allows a very flexible application in which external audio source/sinks can be connected. The example shows an external CD player digital output giving the main Fs audio rate of the whole system. This rate is also the one of the external DACs and an ADC, being configured as slave.
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9.1
Note:
VHI 1 2 VCM
TDA7580
RO = 01KW To prevent Electromagnetic injection 46 ADDITIONAL GPIO 10K(*) VDDH 10K(*) VDDH RO FSYNC
13 220nF
TST3_LRCKR DBRQ1 DBRQ0
RO
VLO 3 6 VCMOP 4.7 m F
57 51
4.7 m F GNDSD 7 44 LRCK0_LRCKT 10nF INP 4
10 m F
4.7 m F
12 VCM
VDDD
31 43 42 GNDD 5 6 SDOUT_SDO0
2
IFOUT1
SCLK0_SCKT SCK
3
RO RO SDATA
220nF
30
470
IFOUT2
5
10nF
9
INM CKREFP 13
26
15pF (*)
Frel+
TDA7535
SO14
8 OUTSL L_Radio F 10m
25
Frel14
470 CKREFN
59 VDD 10F 60 GND VDDA VDDA 10
VDD
GNDA
TDA7515
15
220pF
28 GNDMTR 16
DAGC
470 AGCKEY
14
7
OUTSR R_Audio
33
RESETN 470nF
RSTN
23 22pF I2C BUS SDA
SDA 18
470
SDA_MOSI
TDA7580
TQFP64
54 GNDH
VDD 10F 48 GND 41 VDDH
VDDH
VDDH 100nF
Electrical application scheme
Figure 20. Application diagram example
SCL 20
22 22pF
VDD
SCL SCL_SCK
470
53
47
VDD
VDD 22
10F
GND 21
VDDH
100nF
VDDH 30
11
VDDA
RDS_CS
VDDOSC
40
GNDH
(*) OPTIONAL
470nF
GNDOSC
8 9 10 12
29 31 INT
37
36
34
GPIO_SDO1
TESTN
VDD
VDA and VDD = 1.8V VDDA and VDDH = 3.3V
XTI
5.6pF (**) 10pF 180R
XTO VDDMTR
VDDH
VDD
(**)
10F
35 GND
VDA RANGE 5.6pF TO 10pF 470nF DEPENDING ON BOARD PARASITICS
32
27 VDDH
28 GNDH 100nF
63 VDDH GNDH 100nF
62 VDDSD
64
61 VDDISO
RDS_INT
DSP_INTERRUPT
ADDR_SD
RDS_INTERRUPT {put pull-up on board}
The following application diagram is only an example. For real application setup, it is necessary to refer to the application notes.
VCMOP capacitor (4.7uF) is only needed for CA silicon. This is needed to be consistent with "pin description " in Table 6
VDDH
MASTER/SLAVE SELECTION (STATION DETECTOR AFTER RESET)
VDDH
VDDH
Application diagrams
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Package marking
TDA7580
10
Package marking
Figure 21. Package marking
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TDA7580
Package information
11
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 22. Mechanical, data and package dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K ccc 0.45 11.80 9.80 0.05 1.35 0.17 0.09 11.80 9.80 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 12.20 10.20 0.464 0.386 1.40 0.22 TYP. MAX. 1.60 0.15 1.45 0.27 0.20 12.20 10.20 0.002 0.053 0.055 MIN. TYP. MAX. 0.063 0.006 0.057 inch
OUTLINE AND MECHANICAL DATA
0.0066 0.0086 0.0106 0.0035 0.464 0.386 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0177 0.0236 0.0295 0.0393 0.480 0.401 0.0079 0.480 0.401
0 (min.), 3.5 (min.), 7(max.) 0.080 0.0031
LQFP64 (10 x 10 x 1.4mm)
D D1 A D3 A1 48 49 33 32
0.08mm ccc Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
B
0051434 F
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Revision history
TDA7580
12
Revision history
Table 22.
Date 24-Jan-06 01-Jun-04
Document revision history
Revision 1 2 Initial release. Changed the style look following the "Corporate technical publications design guide. Changed the maturity from product preview to final. Included legend for I/O definition. Included separated specification for the 2 SPI (BSPI and RDS-SPI). Upgraded all tables with temperature range and electrical / timing parameters. Changed description of PIN 6 in PIN description table. Added new sub section titled AM/FM Detector (CORDIC). Updated all tables. Package changed, layout and text modifications Changes
01-Dec-04
3
01-Jan-06 09-Mar-07
4 5
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TDA7580
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